ELECTRONIC DESIGN (ES2610)

Dr. E.L. Hines

Department of Engineering

University of Warwick

.Begin Table C.

Title Page 1

Course Introduction 3

Book List 4

Symbol Table 6

Analogue versus Digital 8

Analogue 13

Digital 15

Typical Transducers 17

Practical Amplifiers 19

Amplifier Classification 19

Amplification and Distortion 19

Practical Considerations 22

Nonlinear Networks 23

Transistors 25

Basic Structure of BJT 25

Basic Structure of JFETs 26

Basic Structure of DE MOSFETs 27

Basic Structure of EMOSFETs 27

Transistor Symbols 28

Modes of Transistor Operation 29

Regions of Operation (BJT) 31

Summary of Biasing Commonly Used with BJTs 31

Summary of Operation of Forward Active BJT 32

Summary of Biasing Conditions for Forward Active Mode for FETs and BJTs 32

Input Characteristics of Forward Active (CE) BJT 33

Output Characteristics of Forward Active (CE) BJT 33

Transfer Characteristic of Forward Active (CE) BJT 34

Output Characteristic of (CS) FET 34

Output Characteristics of Forward Active (CS) JFET/EMOSFET 35

Output Characteristics of Forward Active (CS) DE MOSFET 35

Transfer Characteristics for Three Types of FET 36

Symbols, Characteristics and Voltage Polarities of MOSFETs 37

Symbols, Characteristics and Voltage Polarities of Junction FET 38

Effect of Temperature on BJT Characteristics 39

Typical Parameter Variations (BJT) 41

Effect of Temperature on MOSFET 41

Effect of Temperature on JFET 42

Transistor Biasing for Linear Operation 43

Limitations on Linear Amplification of Bipolar Transistor 44

Limitations on Linear Amplification of FETs 44

Signal Representation on Output Characteristics 45

Simple BJT DC Model (Ebers-Moll) 46

Bias Circuits - BJTs 48

Stability Factors 54

Bias Design 55

FET BIASING 61

(1) JFET and DE MOSFET 61

(2) E MOSFET 61

FET Biasing Circuits 62

JFET Self Bias 62

MOSFET Biasing Circuit 63

DE MOSFET 63

E MOSFET 63

Improved Self Bias Circuit for JFET 65

Improved E MOSFET Bias Circuit 66

Potential Divider Source Resistor 69

Relative Merits of FET Circuits 70

Simple Linear Amplifier 72

Simple Graphical Analysis 72

Graphical Determination of Amplifier Gain from Transistor Characteristics 73

Useful Laws, Theorems and Relationships 75

Network Theorems Appendix 77

Network Theorems 77

Kirchhoff's Current Law (KCL) 77

Kirchoff's Voltage Law (KVL) 77

Norton's Theorem 77

Thevenin's Theorem 78

Source Transformation 80

Source Absorption Theorems 80

Superposition Theorem 81

Practical Voltage Divider 82

Loop (or Mesh) Analysis 83

Generalised Systematic Procedure for Mesh Analysis 83

Node Voltage Analysis 84

Generalised Systematic Procedure for Node Analysis 85

Summary of the Node Voltage Procedure 86

Loop (Mesh) Current versus Node Voltage 86

Determinants and Cramer's Rule 87

Miller's Theorem 90

Miller's Dual 91

Controlled Sources (unilateral) 96

(i) Voltage Controlled Voltage Source (VCVS) or Voltage Amplifier 96

(ii) Current Controlled Current Source (CCCS) or Current Amplifier 97

(iii) Voltage Controlled Current Source (VCCS) or Transconductance Amplifier 98

(iv) Current Controlled Voltage Source (CCVS) or Transresistance Amplifier 98

Effect of Source and Load 99

Two Port Circuits 102

Transmission Parameters 103

Hybrid g Parameters (g_ij) 104

Hybrid h Parameters (h_ij) 104

Short Circuit Admittance Parameters (Y_ij) 105

Open Circuit Impedance Parameters (Z_ij) 105

Parameter Notation (IEEE definition) 106

Further Aspects of Two Ports 106

.End Table C.

Course Introduction

Electronic design

Dr. E.L. Hines Room A305

Autumn term course comprising:-

- 30 hour lecture course (3 hours per week for 10 weeks)

Monday 9 a.m. H051,

Thursday 2 p.m. L4,

Friday 11 a.m. L4.

- 5 three hour lab sessions starting in week 6 (one session per week).

Monday 2-5 p.m. CSE.

Tuesday 2-5 p.m. EE.

Overall assessment based on 50% from lab report and 50% from examination.

The course is structured so that material required for the lab is covered before the labs start, as far as possible.

Therefore some of the material will not be covered in the usual order.

Course broadly covers:

Transistors - Characteristics & Applications

Operational Amplifiers - Characteristics & Applications

Relevant 'glue' for the above

Book List

Allen & Holberg, CMOS analog circuit design, Holt Rhinehart & Winston, 1987, B2.

Banzhaf, Computer-aided circuit analysis using spice, Prentice-Hall Int., 1989, B2.

Barna and Porat, Operational amplifiers, 2nd edition, Wiley, 1989, B2.

Burns & Bond, Principles of Electronic Circuits, West, 1987, B2.

Cathey, Electronic devices and circuits, McGraw-Hill, 1989, B2.

Chua, Desoer & Kuh, Linear and non-linear circuits, McGraw-Hill, 1987, B2.

Franco, Design with operational amplifiers and analog integrated circuits, McGraw-Hill, 1988, B2.

Ghausi, Electronic Devices & Circuits: Discrete & Integrated, Holt-Saunders Int., 1985, B1.

Grant & Gowar, Power MOSFETs: Theory and applications, Wiley, 1989, B1.

Hayes & Horowitz, Student manual for the art of electronics, Camb. Univ. Press, 1989, B2.

Horowitz & Hill, The Art of Electronics (2nd ed.), Cambridge Univ. Press, 1989, B1.

Kennedy, Operational amplifier circuits: theory and applications, Holt Rinehart and Winston, 1987, B2.

Mauro, Engineering Electronics: A practical approach, Prentice-Hall Int., 1989, B1.

Mitchell & Mitchell, Introduction to Electronic Design, Prentice-Hall Int., 1988, B2.

Savant, Roden & Carpenter, Electronic Circuit Design, Addison-Wesley, 1987, B2.

Sedra & Smith, Microelectronic Circuits, 2nd ed., Holt Rinehart & Winston, 1987, B2.

Stanley, Electronic devices circuits and applications, Prentice-Hall Int., 1989, B2.

Stanley, Operational amplifiers with linear integrated circuits (2nd ed.), Merrill, 1989, B1.

Tuinenga, SPICE: A guide to circuit simulation using PSPICE, Prentice-Hall Int., 1988, B2.

Williams, Power electronics devices drivers and applications, Halsted press, 1987, B1.

Yip, High frequency circuit design and measurements, Chapman & Hall, 1990, B2.

Symbol Table

AC Alternating Current

A_CL Closed Loop Gain

ADC Analogue to Digital Convertor

AF Audio Frequency

AGC Automatic Gain Control

A_I Current Gain

A_m Midband Gain

A_OL Open Loop Gain

A_P Power Gain

A_V Voltage Gain

BJT Bipolar Junction Transistor

BW Bandwidth

b=h_FE Current Gain

CAD Computer Aided Design

CB Common Base

CC Common Collector

CD Common Drain

CE Common Emitter

CG Common Gate

CLG Closed Loop Gain

CMOS Complementary Metal Oxide Semiconductor

CMRR Common Mode Rejection Ratio

CS Common Source

DAC Digital to Analogue Convertor

DC Direct Current

ECAD Electronic Computer Aided Design

EMI Electromagnetic Interference

FET Field Effect Transistor

GBWP Gain Bandwidth Product

Ge Germanium

HF High Frequency

Hz Hertz

I_B Base Current

I_BQ Operating Point Base Current

I_C Collector Current

IC Integrated Circuit

I_CBO Collector to Base Reverse Leakage Current

I_CEO Collector to Emitter Reverse Leakage Current

I_CQ Operating Point Collector Current

I_D Drain Current

I_DSS Reverse Leakage Drain Current

I_E Emitter Current

I_G Gate Current

I_OS Offset Current

I_S Source Current for FET, Saturation Current

for BJT

K Boltzmann's Constant

KCL Kirchoff's Current Law

KVL Kirchoff's Voltage Law

LF Low Frequency

LSB Least Significant Bit

MOSFET Metal Oxide Semiconductor Field Effect

Transistor

n Device Constant

NFB Negative Feedback

OA Operational Amplifier

OLG Open Loop Gain

PA Power Amplifier

PCB Printed Circuit Board

PD Potential Difference

P_D Power Dissipation

PFB Positive Feedback

PSRR Power Supply Rejection Ratio

PSU Power Supply Unit

q Electron Charge

Q Transistor Quiescent Operating Point

RF Radio Frequency

RMS Root Mean Square

T Absolute Temperature

Si Silicon

SOA Safe Operating Area

V_BC Base Collector Voltage

V_BE Base Emitter Voltage

V_CC Collector Supply Voltage

V_CE Collector Emitter Voltage

V_DD Drain Supply Voltage

V_DS Drain Source Voltage

V_EE Emitter Supply Voltage

V_GS Gate Source Voltage

V_I Input Voltage

V_O Output Voltage

V_OS Offset Voltage

V_PO Pinch-off Voltage

V_SS Source Supply Voltage

V_T Threshold Voltage or Thermal Voltage

Analogue versus Digital

[Allen&Holberg P3]

Essentially three broad strands:

- Analogue - signal (voltage, current, charge, etc.)

defined over a continuous range of time

and amplitude.

T is the period of the digital or sampled signals.

- Digital - signal which is only defined at discrete

values of time and amplitude.

- Analogue - sampled data signal.

A digital signal is typically a binary weighted sum of signals only having two amplitudes, 0 and 1.

N

D = b₁2^-1 + b₂2^-2 + b₃2^-3 + ... + b_N2^-N = _ b_i2^-i

i=1

Therefore it is possible to implement digital circuits with only two states resulting in regularity and functions which can be defined by algebra.

Thus digital circuit designers can readily design complex circuits.

Diagram Shows A Typical Signal Processing System

Block 1

- filters, automatic gain control (AGC), analogue to

digital conversion (ADC) etc.

- speed and accuracy may dictate

Block 2

- microprocessor resulting in flexibility etc.

Block 3

- filters, amplifiers, digital to analogue conversion

(DAC) etc.

System may be implemented with the objective of:

- maximising analogue content

- maximising digital content

- reaching the best compromise for the application

Generalised Analog Interface

Signal Bandwidths that can be Processed by Present Day Technologies

For signal processing bandwidth (BW) consideration is most important.

Diagram covers 10 orders of magnitude.

Lower end is seismic (does not extend below 1 Hz because of absorption characteristics of the earth).

At upper end are microwaves (not used much above 30 GHz because of signal processing difficulties).

Bandwidths of Signals Used in Signal Processing Applications

Generally for signal processing one can use:

- analogue for frequencies greater than 10 MHz

- digital for frequencies less than 100 KHz

In the overlap there is a trade off between:

- accuracy and flexibility of digital

and

- low cost, power and size of analogue

Typical implementation alternatives:

- BJT for analogue

- MOS for digital because of low power, small size etc.

- CMOS-BJT for mixed-mode because CMOS is more

comparable with the analogue fabrication process

Therefore CMOS-BJT technology is advantageous as a compromise in terms of cost, size, power requirements etc.

whilst maintaining, or slightly improving, performance in terms of bandwidth etc.

Another factor affecting the choice between analogue and digital techniques is the fact that:

over the last decade there has been a growing trend

towards the digitisation of measurement, information

processing and control.

We will briefly consider the advantages and disadvantages of each.

Analogue

Disadvantages

- noise - two sources

(a) internal (due to system components) and

(b) externally generated.

(b) is much stronger and difficult to eliminate although shielding and grounding may minimise it.

Its amplitude may be greater than the signal of interest which may cause problems with filtering, for example.

Synchronous detection and correlation may provide a solution, which remains delicate and expensive.

Continuous nature of the signal is very dependent on the quantitative nature of measured signals, thus the noise problem is very acute because it interferes with the uncertainty of the measured quantity.

Noise influences are largely eliminated in digital systems due to the qualitative quantisation process.

- drift (time dependent displacement of measurement origin) which may be at two levels:

(a) level of parameters of system's components.

Their variations induce changes in linear operating points which leads to parasitic offset voltages.

(b) level of manual adjusting devices (in zero-balancing, balance etc.).

Settings may be modified by mechanical vibrations which induce small potentiometer displacements, or thermal phenomena which lead to dilation of adjusting elements.

Parasitic drift is a worrying matter in analogue design.

It increases costs, often significantly.

Its influence must be minimised by extra compensation devices (drift compensator, automatic zero etc.) by choosing stable components (metal or carbon film resistors etc.), or by design (IC differential amplifiers etc.).

Drift normally makes zero adjustment useless in analogue instrumentation.

In digital systems zero is only defined within a quantum (+/- 1 least siginificant bit (LSB)).

- Difficulty in memorising the measured quantity is a big failing in analogue circuits.

Usually achieved with capacitors whose failings are well known.

Magnetic recorders can be used, in spite of noise and BW limitations.

Access is sequential and therefore slow.

- Risk of instability.

Parasitic coupling can lead to instability in terms of oscillations making the system useless.

This may be caused by temperature variations of parameters which leads to an increase in gain

(closed loop gain > 1 and -180 degrees lag).

- High power consumption.

Higher than digital because operating point of active devices must be maintained in the linear zone.

Advantages

- Transducers are mainly analogue (i.e. deliver analogue voltage or current only).

Only a few quantities such as angular or linear displacement can be directly converted into digits.

- Simplicity of design.

Design models are familiar to designers because of linearity around the operating point.

Modelling is difficult for digital because of discrete nature.

Filters are predominantly analogue at high frequencies, digital filters are limited by the speed of processors.

Waveform generators are predominantly analogue because they are easier to build although amplitude and frequency are sometimes difficult to stabilise.

- Ease of realisation.

Easy to optimise by tweaking variable elements.

Real-time instantaneous values not susceptible to glitches as in digital.

Digital

Disadvantages

- Effect of quantisation and sampling.

Quantisation adds white, un-correlated, noise with RMS q²/12.

Reduce by reducing q (i.e. use more bits).

Nyquist's Shannon's theorem gives theoretical limits on sampling frequency (f_s).

f_s is also limited by quantisation time.

That is, more accuracy needs more samples which leads to more expensive devices and longer conversion times.

- Impossible to access intermediate values.

In analogue systems intermediate values can be monitored.

This is useful at the realisation stage, and if faults occur it is necessary to replace defective elements.

In digital systems this is not possible for two reasons:

(a) word lengths necessitate correct interpretation.

In analogue systems over-flow is not possible because this is limited by the saturation level of the system.

(b) use of complex ICs does not simplify error location.

Advantages

- insensitivity to noise and drift.

Large error margins, makes use of error detection/correction codes.

- Ease of transmission.

Repeater can be used to restore signal levels.

Digital data is regenerated as system complexity increases whereas analogue is degraded.

ADC process is now being performed as close as possible to the transducer.

- Good galvanic insulation.

For analogue use transformers.

Digital much easier, use optocouplers.

- Ease of digital processing.

Low cost family of circuits now available to facilitate digital system design.

- Programming intelligence.

Digital systems can be made intelligent.

For example the choice between strategies, insure safety, allow tight control etc.

May include constant factors, test conditions, iterations etc.

Therefore one can utilise man-machine dialogue to simplify, compared with analogue.

Correction for transducer, using look-up tables for example.

Analog versus Digital

Analog examples:

Voltage Amplifier:

V_o(t) = AV_i(t)

Voltage Divider:

R₂

V_o = ------- V_i

R₁+R₂

In both cases the output is available immediately, almost.

Digital example:

Input V_i

»

V_o = AV_i

»

Output V_o

Output is available after at least 50mS for the simplest calculation.

Typical Transducers

[Mauro P79]

Examples of sources

pH measuring device

tape heads

phonograph cartridge

microphones

Examples of loads

loud speaker

variable resistance loads (need fixed v_o)

complex loads (capacitive/inductive)

N.B. for voltage amplifier R_i >> R_s

for current amplifier R_i << R_s

for impedance matching R_i = R_s

(may need to use transformer because maximum power

to a resistive network does not deliver maximum

power.) R_S maximum power R_T=R_L

AC maximum power Z_L=Z_TH^*; * conjugate.

pH Measuring System (alkalinity/acidity)

v_s is proportional to pH;

R_s is very large and varies with temperature and from

one device to the next.

Therefore we need to amplify voltage/current

independent of R_s.

(for voltage amplifier R_i ³ 10R_s - preferred

for current amplifier R_i ú 10R_s).

Tape Playback Head

i_s proportional to signal on tape;

Z_s (=jwL_s) is impedance of playback coil;

we require voltage amplifier with

R_i << Z_s Þ i_i = i_s

N.B. if R_i is not much smaller than Z_s over the whole frequency range of interest then distortion will occur.

if a voltage amplifier is used then

di_s

v_i = L -----

dt

thus v_o is proportional to the derivative of i_s.

Phonograph Cartridge

Variation of R_s in this case may not be too critical because we can compensate with the gain control.

N.B. if the amplifier was being used in an oscilloscope then R_s variations would of course be intolerable.

Practical Amplifiers

[RJ Smith P298&466]

Amplifier Classification

May be:

(1) Single stage - one amplifying element;

(2) Multi stage - small signal voltage or current

followed by power stage.

Main types

(1) Audio-frequency range » 30 Hz to 20 KHz;

(2) Direct coupled - zero to a few Hz;

(3) Video or wideband - 30 Hz to 4 MHz;

(4) Radio frequency - narrowband (selective).

eg 80 to 100MHz FM

Amplification and Distortion

[RJ Smith P466&481 Ch17]

Voltage gain for sinusoidal signal

V_O

A_v = ---- = Ae^jq

V_I

Two General Responses:-

(1) Linear - A and q are independent of signal

amplifier and frequency.

(2) Non-Linear:-

(i) Amplitude - extra harmonics caused by device or

noise, random noise (snow on TV);

(non-linear characteristic)

(ii) Frequency - bandwidth problems;

(iii) Phase.

Both (ii) and (iii) caused by inductors and capacitors;

ear sensitive to (i) & (ii) not (iii);

eye sensitive to (iii).

Dynamic range limited by (1) noise obscuring signal (2) amplitude distortion.

Practical Considerations

1. Biasing

Transistors kept at quiscent point Q by DC power

supply units (PSUs) (batteries or mains) and biasing

networks.

2. Coupling

Coupling is necessary between stages in amplifiers.

Use resistors and/or capacitors to separate AC

signal and DC bias, and to prevent feedback

3. Load Impedance

Purely resistive for minimum A_v variation with

frequency.

Tuned circuits - usually parallel resonant.

Voltage amplifiers - large load resistor R_C

necessary to drive the load but leads to large

PSUs.

Therefore compromise.

Loads for greater efficiency etc in class A include

inductor, transformer and active.

4. Input and Output Impedance

Cascaded stages interact,

therefore for best results:-

Input impedance should be high to minimise

loading (efficient voltage transfer).

Output impedance should be low for efficient power

transfer.

Voltage versus Current versus Power

amplifiers.

5. Unintentional Elements

Wiring between components can store magnetic or

electric field energy.

(Former important at high frequencies.

Latter can be represented by wiring capacitance.)

Energy storage also occurs in transistors and

detailed models include the effect of junction

capacitance etc.

These are usually omitted at low frequencies.

Definition of the Symbols for Various Signals

Signal Definition Quantity Subscript Example

------------------------------------------------------------

Total instantaneous Lowercase Uppercase i_D

value of the signal

DC value of the signal Uppercase Uppercase I_D

AC value of the signal Lowercase Lowercase i_d

Complex variable, phasor, Uppercase Lowercase I_dm

or RMS value of the signal

Nonlinear Networks

Straight forward application of linear analysis is inappropriate in cases such as:

Use:

(1) Analytical solution: EG

i = a_o + a₁v + a₂v² + a₃v³ + .....

(First two terms leads to linear solution

First three terms leads to practical nonlinear solution)

a₀, a₁, etc. may be found by using simultaneous equations from the v-i characteristics.

(2) Piecewise linearisation:

(3) Graphical solution:

Plot appropriate curves and locate points of intersection. E.g. use of load lines on diode and transistor characteristics.

Transistors

Form basic building bricks in circuits. Current flow between two terminals is controlled by a third terminal.

Two basic types:-

(1) Bipolar - BJT - current controlled;

(2) Unipolar - FET - voltage controlled.

Current flow is mainly due to p-type, n-type or p and n type charge carriers.

npn and n channel are best performers thus they are most popular. (This is because they make use of electron mobility which is high and leads to better frequency response and lower conductance. pnp depends on hole mobility which is lower. Also pnp have poor base width definition which leads to lower current gain.)

Basic Structure of BJT

FET Family Tree

FETs

¦

+---------------------------+

¦ ¦

JFET MESFET MOSFET

(GAs base for GHz range ¦

analogue and digital) ¦

¦ ¦

+--------------+ +----------------+

¦ ¦ ¦ ¦

n-channel p-channel depletion enhancement

¦ ¦

¦ ¦

n-channel ¦

+-----------+

¦ ¦

n-channel p-channel

Basic Structure of JFETs

Basic Structure of DE MOSFETs

Basic Structure of EMOSFETs

Transistor Symbols

Modes of Transistor Operation

Transistors have three terminals. In use two terminals used for signal input and two for signal output (one terminal is common to both input and output).

The three basic methods of connection for BJT are:-

¦ Common Common Common base

¦ emitter collector Wide BW

¦ Medium BW (no Miller effect)

-----------------+------------------------------------------

Voltage gain ¦ high (400) low (<1) high (400)

Current gain ¦ high (50) high (50) low (<1)

Input resistance ¦ medium (1kW) high (200kW) low (50W)

Output resistance¦ high (50kW) low (100W) very high(2MW)

Power ¦ large small medium

For JFET and MOSFET (FETs) there are also three basic methods of connection:-

¦ Common Common Common

¦ source drain gate

-----------------+--------------------------------------

Voltage gain ¦ medium (50) low (<1) medium (50)

Current gain ¦ very high very high low (»1)

Input resistance ¦ very high very high low (50W)

Output resistance¦ high (50kW) low (200W) high (100kW)

Power ¦ large small medium

Most commonly used modes:-

CE for BJT

CS for FET

(we will be using these two unless otherwise stated)

Regions of Operation (BJT)

Transistors effectively consist of two pn junctions. Each of which may be forward or reverse biased. In the case of BJT the four possible regions of operation are used as follows:-

(i) Forward active - amplification;

(ii) Reverse active - rarely used;

(iii) Saturation - ¦

(iv) Cutoff - ¦ logic/switch

Summary of Biasing Commonly Used with BJTs

Summary of Operation of Forward Active BJT

Summary of Biasing Conditions for Forward Active Mode for FETs and BJTs

Input Characteristics of Forward Active (CE) BJT

Output Characteristics of Forward Active (CE) BJT

Transfer Characteristic of Forward Active (CE) BJT

DI_C

b = ----- = h_FE (current gain)

DI_B

Output Characteristic of (CS) FET

N.B. no input characteristic because of high input impedance

JFET reverse biased input, MOS insulated gate, therefore MOS susceptible to static.

JFET I_G = 10^-9

MOS I_G = 10^-12

Output Characteristics of Forward Active (CS) JFET/EMOSFET

Output Characteristics of Forward Active (CS) DE MOSFET

Transfer Characteristics for Three Types of FET

DI_D

g_m = ------ (transconductance)

DV_GS

N.B. typically parabolic in all three casese.

FET characteristics (saturation region)

(a) For depletion and depletion/enhancement mode devices

i_D = I_DSS(1 - V_GS/V_PO)²

where i_D=drain current in constant current region,

I_DSS=i_D when V_GS=0,

V_PO=pinch-off voltage.

(b) For enhancement only MOSFET

i_D = K(V_GS - V_T)²

where K=device parameter and V_T=turn-on or threshold voltage.

Symbols, Characteristics and Voltage Polarities of MOSFETs

N.B. Substrate terminal may be connected to source or elsewhere.

Symbols, Characteristics and Voltage Polarities of Junction FET

Effect of Temperature on BJT Characteristics

[King P68]

Effect on Input of BJT in CE Mode

Forward current across junction increases exponentially with temperature v_BE decreases with increase in temperature.

For fixed i_B get different v_BE.

Effect on Output of BJT in CE Mode

For fixed i_B get different i_C.

effect on b

D i_C

b = h_FE » ------ [ Slope of transfer

D i_B charcteristics ]

b generally tends to increase with increasing temperature.

Effect on I_CBO

Reverse saturation collector to base current (I_CBO) increases exponentially with temperature (effect often neglected with Si devices).

Typical Parameter Variations (BJT)

(1) | V_BE | decreases by 2.5 mV/^oC.

(2) b may vary by 6:1 and increases linearly with

temperature.

(3) I_CBO may vary by 10:1 and approximately doubles for

every 10 ^oC rise above 25 ^oC.

(4) PSU variations.

Effect of Temperature on MOSFET

Main effect is variation in saturation i_D for a given v_GS.

As temperature increases i_D falls.

Measurements show :-

i_D Á T^-2

Effect on Transfer Characteristics

Effect of Temperature on JFET

i_G increases with temperature (compare with reverse biased diode).

I_DSS is strongly temperature dependent.

V_PO is weakly temperature dependent.

Since transfer characteristic of JFET & MOSFET are temperature dependent then

D i_D

g_m (= ------ ) also temperature dependent.

D v_GS

Effect on Transconductance

Transistor Biasing for Linear Operation

[Floyd]

Objective: place transistor in forward active region.

Requires : Base-emitter junction forward biased,

Base-collector junction reverse biased.

Two broad aspects:-

(1) Setting operating point, Q, in forward active region at such a position so as to be within the safe operating region specified by the maximum dissipation hyperbola, i.e. device power dissipation given by:

(P_D)_max = V_CEI_C - BJT

or (P_D)_max = V_DSI_D - FET

V_CE ú (V_CE)_max and I_C ú (I_C)_max

V_DS ú (V_DS)_max and I_D ú (I_D)_max

(P_D)_max generally decreases with increasing temperature

(See environmental and thermal considerations)

Limitations on Linear Amplification of Bipolar Transistor

[King P120]

Limitations on Linear Amplification of FETs

(2) Having set Q the problem is then to maintain it despite variations in temperature and among devices of the same type. This must be achieved without adversely affecting the desired circuit performance.

Problem is difficult because:-

(a) Wide variations in device parameters expected in mass-produced transistors.

(b) Complicated inter-relations among transistor variables.

(c) Inherent sensitivity of semiconductor devices to temperature.

[Schilling and Belore P174]

- b, I_CBO and V_BE may vary due to temperature variation

- PSU variations due to imperfect regulation

- Variations in circuit resistance due to tolerance

and/or temperature effects.

We will be looking at a few of the biasing techniques available to combat the biasing problem.

Objective: design a circuit to amplify an AC signal without distortion, or a shift of operating region and biasing point.

Signal Representation on Output Characteristics

Simple BJT DC Model (Ebers-Moll)

[Ashburn]

qV_BE

forward current I_F = I_ES (exp ------ - 1)

KT

qV_BC

reverse current I_R = I_CS (exp ------ - l)

KT

Reciprocity relationship relates the short circuit saturation currents to the common base current gains

I_S = Á_FI_ES = Á_RI_CS

The 3 terminal currents are given by

I_C = Á_FI_F - I_R

I_E = Á_RI_R - I_F

I_B = (1- Á_F)I_F + (1 - Á_R)I_R

Ideal diodes model exponential relationship. Current generators model transistor action due to the narrow base region.

(The model is suitable for saturation region as well.)

Recombination in the emitter base depletion region is not modelled in this basic E-M model.

Bias Circuits - BJTs

[Morris P50]

(1) Basic Bias Circuit

Base current, I_B, derived from V_CC via R_B using Kirchoffs Voltage Law (KVL)

I_BR_B = V_CC - V_BE

V_CC - V_BE

\ I_B = ---------

R_B

V_BE is forward conduction potential difference (PD) across the base-emitter junction, this can usually be neglected compared with V_CC.

Hence I_B » V_CC/R_B

Collector current, I_C, is given by

V_BC/V_T

I_C = bI_B + I_CBO(e - 1)

= bI_B + I_CBO(b+1)

= ÁI_E + I_CEO

where I_CBO is the reverse leakage current of base-collector junction and V_T is the thermal voltage = KT/q = 25mV.

For Si device this can be neglected thus

I_C » bI_B

Hence I_C » b V_CC/R_B

In class A operation for maximum signal swing the voltage across R_C should be about half the supply voltage

V_CC V_CC

\ I_CR_C = ----- Þ R_C = -----

2 2I_C

The main disadvantage of this circuit is that it does not compensate for the effects of temperature on the transistors parameters. Especially:

(a) current gain - b ;

(b) leakage current - I_CBO (mainly with Ge);

(c) Base-emitter voltage - V_BE

Net effect of short-comings in previous circuit is "drift" in collector current and hence voltage. In voltage amplifiers this has the effect of shifting Q. Which leads to changes in amplifier constants, such as gain input and output impedance etc. In power amplifiers increased I_C can lead to a regenerative process with junction temperature known as "thermal runaway".

(2) Emitter Resistor Bias

This circuit offers some improvements in thermal stability because of R_E. (We are only interested in DC changes for biasing, hence C_E could be included to shunt AC across R_E. This is usually achieved by making X_E ú R_E/10 at the lowest frequency of interest.) As temperature increases the net effect of parameter changes is for I_C to increase, therefore V_E also increases. If V_E increases it leads to V_BE decrease, I_B increase (because of less forward bias) and I_C decrease.

Hence this circuit is quite stable to temperature changes.

(3) Collector Feedback Bias Circuit

For circuit shown, if V_CE >> V_BE then

V_CE

I_B » -------

R_B

Hence if the temperature increases then I_C increases leads to decrease in V_CE. Therefore, I_B decrease hence reducing I_C to a value lower than it would be without the bias.

Stability could be further improved by the addition of R_E.

Basic equations for circuit are:

I_C = bI_B = b V_CE/R_B

R_C

and V_CE = V_CC - I_CR_C = V_CC - bV_CE ----

R_B

bR_C

\ R_B = -------------

V_CC

( ----- - 1 )

V_CE

If V_CE = V_CC/2

then R_B = bR_C.

Unfortunately R_B provides AC as well as DC feedback which reduces the overall gain. To limit this effect of feedback at signal frequencies R_B can be replaced by two series resistors and the junction of the two is decoupled to OV by a capacitor.

Example:

This causes R₁ to shunt the input and R₂ the output.

N.B. Gain versus BW trade off

(4) Potential Divider and Emitter Resistor Bias

Further improvement in thermal stability is brought about by the use of the above circuit. I_B is supplied by R₁R₂, while R_E provides V_E which increases with temperature. The current drawn by R₁ and R₂ should be of the order of ten times I_BQ (ensuring that the potential at the junction of R₁R₂ remains constant even when I_BQ changes slightly. When temperature increases, I_E also tends to increase initially due to the increase in I_C, but I_B remains constant due to R₁R₂. This leads to a lower V_BE with increase in temperature, thus compensating for an increase in temperature by a decrease in I_B. This leads to a decrease in I_C to its normal value.

Thermal stability can be further increased by including a forward biased diode in series with R₂. Effect of increase in temperature on diode D would be to decrease forward PD by about 2.5 mV/^oC, so voltage at R₁R₂ junction decreases with increasing temperature. Both devices should be made of same material.

Gain stability can be improved by splitting R_E as shown. R_E1+R_E2 used in DC biasing, but only R_E1 used in AC operation to swamp r_e which leads to gain stability (because r_e would vary with I_E » I_C).

-R_C 25

A_V = --------- ( r_e= -------- )

R_E1 + r_e I_E(mA)

Analysis/design of the potential divider circuit may be facilitated by using its Thevenin's equivalent:-

R₁R₂ R₂

where R_T = ------- and V_T = -------- V_CC

R₁ + R₂ R₁ + R₂

[ R_in = (b+1)R_E » bR_E if R₁ __ R₂ << R_in ignore effect ]

As we will see design of the circuit is usually a compromise between several factors. For good thermal stability R_E should be large, but this leads to an increased power loss and limited output voltage swing. If R_E is small then temperature stability suffers. V_E should be 0.1 to 0.3 times V_CC and R₂ should be 10-20 times R_E.

Example:

Determine the region of operation and all node voltages and branch currents. V_CC = 10V, V_BB = 4V, R_C =4.7K, R_E = 3.3K and b = 100.

Assume forward active and verify. If not forward active try others.

B connected to 4V and E to 0V through R_E, therefore assume V_BE = 0.7V forward bias

\ V_E = V_BB - V_BE = 4 - 0.7 = 3.3V

V_E - 0

I_E = -------- = 3.3/3.3 = 1mA

R_E

C connected to V_CC via R_C, therefore should be reverse biased (i.e. device in active region)

b 100

I_C = ÁI_E = ----- I_E » ------ 0.1 = 0.99mA

1+b 101

Using KVL V_C = V_CC - I_CR_C = 10 - 0.99 * 4.7 = 5.3V

Since V_BB = 4 the base collector junction is reverse biased by 1.3V

Therefore transistor is in forward active region.

I_E 1

Finally I_B » ----- = ----- = 0.01mA

b+1 101

Stability Factors

DI_C

S(I_CBO) = -------

DI_CBO

DI_C

S(V_BE) = ------

DV_BE

DI_C

S(b) = -----

Db

Ideally, stability factor should » 0. If not:

DI_C = DI_CBO*S(I_CBO) + DV_BE*S(V_BE) + Db*S(b)

For potential divider emitter resistor circuit:

(b+1)(1+R_B/R_E) R_E + R_B

S(I_CBO) = --------------- » -----------

(b+1) + R_B/R_E R_E + R_B/b

-b

S(V_BE) = -------------

R_B + R_E(b+1)

I_C1 S₂(I_CBO)

S(b) = --------------

b₁b₂

where R_B=R₁__ R₂, I_C1= initial value of I_C, b₁= initial value of b, b₂= new value of b, S₂(I_CBO)= value of S(I_CBO) for b=b₂.

Now

R_B

(1) S(I_CBO) » 1 + ----- if R_E >> R_B/b

R_E

and we have conflicting requirements for a low value i.e.

(1) Small R_B leads to loading of the signal source,

(2) Large R_E leads to limited output voltage swing.

Therefore, need to compromise.

(2) S(V_BE) » -1/R_E if (b+1) R_E >> R_B

Therefore, we require a large R_E for good stability

I_C1 R_B

(3) S(b) = ----- -----------

b₁ R_B + b₂R_E

Therefore, again we require a large RE for good stability.

Potential Divider Emitter Resistor Bias Circuit

I_C is independent of I_CBO

if V_BB - V_BE >> I_CBOR_B.

I_C is independent of b

if R_E >> R_B/b.

I_C is independent of V_BE

if V_BB >> V_BE.

N.B. Stability requirements may interact with thermal considerations (see later)

Bias Design

(1) Select appropriate nominal Q (I_C, I_B & V_CE) from

data sheet.

(2) Assume V_E = I_ER_E » I_CR_E » 0.25V_CC and solve for R_E.

(3) Select V_CC and R_C

(a) If V_CC specified, R_C » (V_CC-V_CE-V_E)/I_C;

(b) If R_C specified, V_CC » V_E + V_CE + I_CR_C.

(4) Select R_B » (b_minR_E)/10.

(5) Calculate V_BB = I_BR_B + V_BE + (I_B+I_C) R_E

(use I_B = I_C/b, V_BE = 0.7 for Si.)

(6) Calculate R₂ and R₁,

V_CC R₂R_B

R₂ = R_B --------- and R₁ = -------

(V_CC-V_BB) R₂ - R_B

R₂

[ V_BB = ------- V_CC and R_B = R₁ || R₂ ]

R₁ + R₂

Example:

Determine the region of operation and all node voltages and branch currents. b = 100, R_B1 = 100K, R_B2 = 50K, R_C = 5K, R_E = 3K and V_CC = 15V.

Assume active region and apply Thevenin

R_B2 15x50

V_T = V_CC --------- = -------- = 5V

R_B1+R_B2 100+50

R_T = R_B1 __ R_B2 = 100 __ 50 = 33.3K

Apply KVL around input loop

I_E

V_T = I_BR_T + V_BE + I_ER_E but I_B » ------

b+1

V_T-V_BE 5-0.7

\ I_E = --------------- = ------------ = 1.29mA

R_E+[R_T/(b+1)] 3+33.3/101

\ I_B = 1.29/101 = 0.0128mA

Voltage at B V_B = V_BE + I_ER_E = 0.7 + 1.29 * 3 = 4.57V

If active mode I_C = ÁI_E = 0.99 * 1.29 = 1.28mA

Voltage at C V_C = V_CC - I_CR_C = 15 - 1.28 * 5 = 8.6V

V_C is 4.03V higher than V_B.

Therefore transistor is in forward active region.

Example:

Design a potential divider emitter resistor amplifier bias circuit and investigate the effects of b spread on the operating point in terms of (1) I_C and (2) V_CE.

You may assume the following:

- b is typically 50, but may vary between 25 and 75.

- V_CC=15V, the bias conditions are V_CE=5V and I_C=1mA.

- Equal volt drops across R_C, V_CE and R_E, V_BE=0.7V.

Comment on the results.

¦¦¦

Use b=50 to start

V_E = V_CE = V_C = 5

V_C 5

\ R_C = ---- = ----- = 5K

I_C 1mA

V_E = (I_C + I_B)R_E but I_B » I_C/b

\ V_E = (I_C + I_C/b)R_E

\ R_E = V_E/(I_C + I_C/b) = 4.9K

For good stability assume I₂>>I_B e.g. I₂=I_C=1mA

5 + 0.7

\ R₂ = V_B/I₂ = (V_E + V_BE)/I₂ = --------- = 5.7K

1mA

I_B = I_C/b = 20mA

R₁ = (V_CC - V_B)/(I₂ + I_B) = 9.1K

For thevenin circuit

R₂

V_T = V_CC ------- = 5.8V

R₁+R₂

and R_T = R₁ __ R₂ = 3.5K

Effect of b variation

(1) I_C

V_T = I_BR_T + V_BE + R_E(I_B + I_C)

I_C I_C

= ---- R_T + V_BE + R_E( ---- + I_C)

b b

R_T

V_T - V_BE = I_C [ ---- + R_E(1/b + 1) ]

b

\ I_C = (V_T - V_BE) / [R_T/b + R_E(1/b + 1)]

For b = 25 I_C = 0.97mA

For b = 75 I_C = 1.02mA

(2) V_CE

V_CE = V_CC - I_CR_C - R_E(I_B + I_C)

= V_CC - I_CR_C - R_E(I_C/b + I_C)

For b = 25 V_CE = 5.2V

For b = 75 V_CE = 4.9V

The circuit Q point is remarkably stable to variations in values of b !!

5% change on I_C -+ For 200%

6% change on V_CE -+ increase in b

Easily good enough for "first order" models !!

Example:

The silicon transistor shown below has the following maximum ratings: P_D(max)=0.8W, V_CE(max)=15V, I_C(max)=100mA, V_CB(max)=20V and V_EB(max)=10V. Determine the maximum value to which V_CC can be adjusted without exceeding a rating. Which rating would be exceeded first? (R_C=1KW, R_B=22KW, V_BB=5V, b_dc=100)

Find I_B

V_BB-V_BE 5V-0.7V

I_B= --------- = --------- = 195.5mA

R_B 22KW

I_C= b_dcI_B = 100 * 195.5mA=19.55mA

I_C is much less than I_C(max) and will not change with V_CC. It is determined by I_B and b_dc.

Voltage drop across R_C is

V_RC=I_CR_C=19.55mA * 1KW=19.55V

Now V_CC(max) occurs when V_CE is a maximum.

\ V_CC(max) = V_CE(max) + V_RC

= 15V + 19.55V = 34.55V

\ V_CC can be increased to 34.55V before V_CE(max) is exceeded.

But has P_D(max) been exceeded at this point?

P_D(max) = V_CE(max)I_C

= 15V * 19.55mA = 0.293W

\ P_D(max) has not been exceeded with V_CC=34.55V.

Hence V_CE(max) is the limiting rating in this case.

N.B. if I_B is removed, causing the transistor to turn off. V_CE(max) will be exceeded because V_CC will be dropped across the transistor.

FET BIASING

Summary of Useful Saturation Region FET Equations

(1) JFET and DE MOSFET

_ V_DS _ ³ _ V_PO _ - _ V_GS _

V_GS

i_D = I_DSS ( 1 - ----- )²

V_PO

¶i_D I_DSS V_GS

g_m = ----- = -2 ------ (1 - ----- )

¶v_GS V_PO V_PO

V_GS

= g_m0 (1 - -----)

V_PO

2I_DSS

Where g_m0 = --------- (i.e. value of g_m at V_GS=0, I_D=I_DSS)

_ V_PO _

(2) E MOSFET

_ V_DS _ ³ _ V_GS - V_T _

i_D = K (V_GS - V_T)²

\ g_m = +2K (V_GS - V_T)

DC model of CS FET is

Generally speaking the DC characteristics of FETs are not as temperature dependent as those of BJTs. If the circuit is designed to work at the highest temperature, then it should also work at the lowest. Design is further simplified by the fact that the input circuit does not draw any DC current therefore it can be neglected. However, variability from device to device must be accounted for.

As far as biasing circuits are concerned, good results are usually obtained by using FETs in the common source equivalent of the common emitter potential divider emitter resistor circuit already discussed. However, for completeness we will look briefly at several special FET circuits.

An important aspect of biasing is to minimise the slope of the bias line obtained by analysing the G-S loop [Bogart P241]

FET Biasing Circuits

JFET Self Bias

For n-channel device the gate to source junction is reverse biased by negative V_GS. Gate is approximately at OV due to R_G. (Small reverse leakage current I_GSS can be neglected.)

I_S(»I_D) leads to volt drop, V_S, across R_S and makes source, S, positive with respect to 0V.

\ V_GS = -I_D R_S

KVL across the output gives:-

V_DS = V_DD - I_D (R_D+R_S).

MOSFET Biasing Circuit

DE MOSFET

Device can operate with positive or negative V_GS, therefore simple bias circuit shown with V_GS=0. KVL across the output gives:

V_DS = V_DD - I_D R_D.

Device operates between turn on and break down, where I_D is nearly independent of V_DS. R_G allows any charge that might build up on the highly insulated gate to "leak off".