.Begin Table C.

Power Amplifiers 249

Amplifier Classification 250

Class A 250

Class B 250

Class AB 251

Class C 251

Class D 252

Amplifier Efficiency 252

Distortion Considerations 253

Elimination of Even Harmonic terms in Class AB and B 255

Resonance 256

Parallel Resonance 256

Series Resonance 257

Normalised Response 259

Bandwidth 260

Class A 261

Inductive Coupling 262

Transformer Coupling 263

BJT Power Dissipation (P_D) 265

Class A Amplifier Current Drain 266

Efficiency for Class A Series Fed Amplifier 266

Class A Efficiency Discussions 267

Class B 269

Class C 272

Class C Amplitude Modulator 276

Class D 277

Integrated Circuit (IC) Power Amplifiers 280

Environmental and Thermal Considerations 280

Thermal Considerations 280

Power Derating Curve 282

Effect of Heat Sink 282

Heat Sink Comments 282

Safe Operating Area (SOA) for Power BJTs 283

Parameter Values of Power Transistors 283

Effect of Temperature on Power MOSFETs 284

Thermal Stability 285

Transistor Switch 286

Simple Switching with Transistors 286

Transistor Switching Waveforms 288

Propagation Delay 288

Speed-up Capacitor 290

Schottky Diode and Emitter Coupling 291

The enhancement MOSFET as a switch 292

CMOS Inverter 292

Switching Inductive Loads 293

Relative Merits of BJTs and FETs 296

Comparison of MOS and Bipolar Power Transistors 297

Operational Amplifier 299

Advantages of IC Operational Amplifier (OA) 300

Ideal versus Typical Characteristics 300

Ideal Models of OA 301

Minimisation of Shortcomings 302

741 example 302

OA Characteristics 304

DC Characteristics 304

Bias Currents 304

Offset Current 305

Offset Voltage 305

External Balancing Techniques 306

Drift 307

Common Mode Rejection Ratio (CMRR) 307

AC Characteristics 309

Gain Bandwidth Product (GBWP) 309

Stability Consideration (Gain and Phase Margins) 311

Rise Time 311

Slew Rate 312

Full Power Response 313

Phase Shift 313

Settling Time 313

Noise 314

Power Supply Considerations 314

Operational Amplifier Protection Circuits 316

Power Supply Rejection Ratio (PSRR) 317

OA Circuits 318

Open Loop 318

Non-Inverting 318

Inverting 319

Closed Loop Operation 320

Effects of NFB 321

Stabilising Gain 321

Stabilising Operation 321

Improving Frequency Response 321

Improving Impedance Characteristics 321

Reducing Distortion 322

Inverting Amplifier 322

Non-Inverting Amplifier 323

Effect of Non-Infinite Open Loop Gain 323

Inverting Amplifier 323

Noninvertiong Amplifier 323

Effect of Input and Output Impedance 324

Noninverting amplifier 324

Inverting amplifier 324

Effect of Bias and Offset Current and Offset Voltage 325

Voltage Follower 325

Inverting Summer 326

Differential Amplifier 327

Bridge Amplifier 328

Integrator 329

Typical Application of Integrator 330

Differentiator 331

Typical Application of Differentiator 331

Voltage to Current Converter 332

Inverting 332

Non-Inverting 332

AC Amplifiers 333

Inverting AC Amplifier 333

Non-Inverting AC Amplifier 333

Bootstrap AC Amplifier 334

AC Amplifiers with Single Supply Voltage 335

Single Supply Inverting AC Amplifier 335

Single Supply Noninverting AC Amplifier 336

Logarithmic Amplifier 336

Alternative Implementations 338

Antilogarithmic Amplifier 339

Ideal Rectifier 339

Improved Half-Wave Rectifier 340

Full-Wave Rectifier 341

Peak Detector 341

Phase Shift Circuits 342

All Pass Lag Network 343

All Pass Lead Network 344

Positive Feedback (PFB) 344

Regenerative Comparator 345

Schmitt Trigger 345

Astable Multivibrator 347

Monostable Multivibrator 348

Sine Wave Generators 350

Requirements for Sinusoidal Oscillations 350

RC Oscillators 351

Wein-Bridge Oscillator 351

Phase-Shift Sinewave Generator 351

LC Oscillators 352

Colpitts Oscillator 352

Hartley Oscillator 353

Crystal Oscillator 353

The 555 Timer 355

Monostable 355

Astable 356

Cascode Configuration 357

.End Table C.

Power Amplifiers

[Chirilian P771]

Designed to deliver large power. Therefore need to be able to dissipate large power in order to minimise temperature build up and possible catastrophe.

Typical devices have large surface areas for effective heat transfer.

Usually employed as the output stage - therefore preceded by impedance matching circuits etc.

Typical applications include:

audio - radio, TV, phono etc where the load is a

speaker.

electromechanical control to drive electric motors.

e.g. disks, tapes, robotic manipulators, process

controllers etc.

Typically requires large signal operation of transistors; i.e. operation over the entire range of the output characteristics (compared with small signals where b, r_e etc are nearly constant).

There are two important consequences:

(1) Change in amplifier characteristic with signal level may lead to distortion which we may need to minimise via feedback etc.

(2) Small signal models are not really appropriate. We may use average values or graphical techniques.

N.B. large signal also describe digital switching circuits but in operation most time is spent outside the active region, therefore power dissipation is very small because either v_CE » 0 or i_C » 0, i.e. in saturation or cut off.

Typical Values for the Hybrid-p Parameters for BJT Small-Signal and Power Transistors

[Mauro]

Parameter Small-Signal Transistor Power Transistor

----------------------------------------------------------

g_m 40-400mS 400-4000mS

C_b'_c 0.2-10pF 5-500pF

C_b'_e 0.5-200pF 50-1000pF

f_T 100 MHz-1GHz 5-150MHz

f_b 1-100MHz 50 KHz-15MHz

r_b'_e 0.3-15KW 25-500W

r_bb' 10-500W 0.1-10W

power < 1 watt >1 watt

Amplifier Classification

[Bogart]

It has been tacitly assumed in all our previous design and analysis that the transistor is biased in the middle of its operating region. This is not always the case with power circuits, and a classification (A, B, AB, C and D) has evolved to describe amplifier operation, dependent on the type of biasing employed.

Class A

A class A amplifier is one in which the operating point and input signal are such that the current in the output circuit (in the collector or drain electrode) flows at all times. A class A amplifier operates essentially over a linear portion of its characteristic.

Class B

A class B amplifier is one in which the operating point is at an extreme end of its characteristic, so that the quiescent power is very small. Hence either the quiescent current or voltage is approximately zero. If the signal excitation is sinusoidal, amplification takes place for only one half of a cycle.

Class AB

A class AB amplifier is one operating between the two extremes defined for class A and class B. Hence the output signal is zero for part but less than one half of an input sinusoidal signal cycle.

Summary of Class A, AB and B

Class C

A class C amplifier is one in which the operating point is chosen so that the output current (or voltage) is zero for more than one half of an input sinusoidal signal cycle.

Class D

Is a switched mode of operation. Here the amplifier's output is switched between cut-off and saturation. So the only time spent in the active region is during the transition.

So as you go from class A through to class D amplifiers, less time is spent in the linear region of operation.

Amplifier Efficiency

In order to compare the relative performance of these different classes of amplifier, a figure of merit known as the "conversion" or "theoretical" efficiency is used. This is defined as

signal power delivered to the load

h = ----------------------------------------- * 100

DC power supplied to the output circuit

The following table summarises the values for theoretical efficiency.

Class ¦ h (%)

-------------+---------------

A ¦ 25-50

B ¦ 78

AB ¦ 25-78

C ¦ 100

D ¦ 100

(Note that these figures represent the theoretical maximum. At the upper limits inductors/transformers are used)

Distortion Considerations

[Bogart P670,675, M&G P799, and Chirilian P151]

- due to nonlinearities in the operating range of an amplifier.

- Clipping at cutoff and saturation due to amplifier being overdriven (too large an input signal) about a centered Q-point.

Input and output waveforms illustrating the deed-zone/crossover distortion

Harmonic Distortion

[Bogart P670, M&G P799, Chirilian P151]

For an input signal of the form

i_b = I_bm cos(wt)

For a linear amplifier the output would be

i_c = Gi_b

where G is the gain

More accurately we have a nonlinear response of the form

i_c = G₁i_b + G₂i_b² + G₃i_b³ + ...

This can be represented as

i_c = I_c+B₀+B₁cos(wt)+B₂cos(2wt)+B₃cos(3wt)

Distortion terms are then defined as

_ B₂ _ _ B₃ _

D₂ º -------- , D₃ º -------- etc

_ B₁ _ _ B₁ _

The total harmonic distortion or distortion factor is then defined as

D º (D₂² + D₃² + .....)^1/2

D is sometimes quoted as a percentage.

Elimination of Even Harmonic terms in Class AB and B

NB in the case of class B and AB we have

i₁ = I_c+B₀+B₁cos(wt)+B₂cos(2wt)+B₃cos(3wt)+ ...

and

i₂ = I_c+B₀+B₁cos(wt+p)+B₂cos2(wt+p)+ ...

= I_c+B₀-B₁cos(wt)+B₂cos(2wt)-B₃cos(3wt)+ ...

i_L = i₁ - i₂ = 2(B₁cos(wt)+B₃cos(3wt)+ ...)

Thus matched transistors eliminates even harmonic terms.

Intermodulation Distortion

If we assume that the output is related to the input by the simple parabolic relationship

i_c = G₁i_b + G₂i_b²

Then it can be shown that if the input contains two frequency components w₁ and w₂.

The output will consist of a DC term and sinusoidal components of frequencies w₁, w₂, 2w₁, 2w₂, w₁+w₂, and w₁-w₂.

The terms w₁+w₂ and w₁-w₂ are the "intermodulation" or "combination" frequencies.

Resonance

Parallel Resonance

1

Y = G + jwC + -----

jwL

1

= G + j(wC - ----)

wL

_ Y _ = [ G²+(wC-1/wL)² ]^1/2 ,

wC-1/wL

q_Y = tan^-1 ---------

G

The frequency at which the susceptances cancel and the admittance is purely conductive is w₀; and q_Y=0 and

(w₀C-1/w₀L)=0

1 1

\ w₀= ------- rads^-1 or f₀ = --------- Hz

Ö(LC) 2pÖ(LC)

(By definition Y₀=G and q_Y=0 at reasonance.)

At LF the susceptance of L dominates and Y increases as frequency decreases and q_Y « -90o.»At HF the susceptance of C dominates and Y increases as frequency increases and q_Y « 90o.»

The frequency response of a parallel GCL circuit

I_C = w₀CV₀ = w₀CI/G = w₀(C/G)I = Q_pI

I_L = V₀/w₀L = I/w₀LG = w₀CI/G = Q_pI

Basic Definition of Q

The quality or selectivity factor Q is a measure of the energy storage property of a circuit in relation to its energy dissipation property. That is

maximum energy stored

Q = 2p -----------------------------

energy dissipated per cycle

It can be shown that for a parallel resonant circuit Q is given by

w₀C 1

Q_p = ----- = ------

G w₀LG

Series Resonance

1 1

Z = R + jwL + ----- = R + j(wL - ----)

jwC wC

_ Z _ = [ R²+(wL-1/wC)² ]^1/2 ,

wL-1/wC

q_Z= tan^-1 ---------

R

The resonance frequency is that at which the impedance is purely resistive i.e. Z=R, q_Z=0 and (w₀L-1/w₀C)=0

1 1

\ w₀ = ------- rads^-1 or f₀ = -------- Hz

Ö(LC) 2pÖ(LC)

At LF capacitive effects dominate and impedance increases as frequency decreases and q_Z « -90o.»

At HF inductive effects dominate and impedance increases as frequency increases and q_Z « 90o.»

The frequency response of a series RLC circuit

V_L = w₀LI₀ = w₀LV/R

V_C = I₀/w₀C = V/w₀CR = w₀LV/R = V_L

For series resonance it can be shown that

w₀L 1

Q_S = ----- = ------

R w₀CR

(For the same component values Q_s = 1/Q_p)

If inductor and capacitor are held constant and resistor is varied then:

If resistor increases, Q decreases - reduced selectivity

If resistor decreases, Q increases - increased selectivity

If resistor is held constant and either inductor or capacitor is increased then we get a shift in w₀ but Q remains the same.

Normalised Response

The response curve of all resonant circuits have the same basic shape therefore it is possible to derive a simple general equation that describes series and parallel circuits which are resonant at high and low frequencies with large and small energy dissipation. To eliminate the effect of specific parameter values, dimensionless ratios are used.

For a series RLC circuit

Z = R + j(wL-1/wC) = 1/Y

at resonance Z₀ = R = 1/Y₀

Y Z₀ R 1

\ ---- = ---- = ---------------- = ---------------------

Y₀ Z R + j(wL-1/wC) 1 + j(wL/R - 1/wCR)

If we introduce a factor w₀/w₀ and substitute Q = w₀L/R = 1/w₀CR

Y 1 1

---- = ------------------------------- = -----------------

Y₀ wL w₀ 1 w₀ w w₀

1 + j(---- ---- - ----- ----) 1 + jQ(--- - ---)

R w₀ wCR w₀ w₀ w

(This equation also describes the impedance ratio Z/Z₀ for parallel GCL circuits.)

Bandwidth

At the corner frequency for Y/Y₀ we get

w w₀

Q(---- - ----) = ± 1

w₀ w

Hence we have two frequencies w₁ and w₂ such that

w₁ w₀ -1 w₂ w₀ 1

---- - ---- = ----- and ---- - ---- = ---

w₀ w₁ Q w₀ w₂ Q

Hence

1 w₀

w₁ = w₀ [ 1+(----)² ]^1/2 - ----

2Q 2Q

and

1 w₀

w₂ = w₀ [ 1+(----)² ]^1/2 + ----

2Q 2Q

The bandwidth is therefore given by

w₀ f₀

BW = w₂-w₁ = ---- or f₂-f₁ = ----

Q Q

(That is bandwidth Á 1/Q)

If Q ³ 10 then [ 1+(1/2Q)² ]^1/2 » 1

1 1

\ w₁ = w₀(1 - ----) and w₂ = w₀(1 + ----)

2Q 2Q

Class A

Efficiency tends to be low because of the high value of DC current compared with the output signal current.

Class A is suitable for fairly low power output applications. Larger signal output or non-centred operating point may lead to distortion. That is, harmonic, cut-off or saturation.

R_DC = R_C + R_E

R_AC = R_C __ R_L

[Bogart P658]

Transformer blocks DC current flow in the load and provides impedance matching for maximum power transfer.

N.B. I_C should not be large enough to saturate transformer and V_CEmax > 2V_CC.

The use of resistive loads as the output stage of power amplifiers (PAs) generally suffers from three main limitations:

(i) Total possible voltage swing is limited because of

the voltage drop across the collector resistor R_C.

(ii) Substantial amount of power is dissipated by R_C.

(iii) Large currents may need to be passed through the

load.

Optimise performance by using inductors or transformers to couple to the load.

Inductive Coupling

[Savant et al P243]

Inductor should be chosen so that at signal frequencies it » open circuit and at DC it » short circuit.

That is wL >> R_L at the lowest frequency

R_coil << R_L and

R_coil << R_E

For maximum output swing

V_CC

I_CQ = -----------

R_AC + R_DC

(where R_AC » R_L and R_DC » R_E)

At I_CQ = V_CEQ/R_L we therefore have

V_CCR_L

V_CEQ = --------- » V_CC if R_E << R_L

R_E + R_L

Therefore output swing » 2V_CC

This is due to the fact that the inductor stores energy during conduction and therefore acts like a second voltage source V_CC.

L also leads to an increase in efficiency compared with the use of RC. (» 50% i.e. twice as efficient).

Transformer Coupling

Design calculations may be simplified by the use of the following relationships:-

Discussion for transformer is similar to use of inductor again h=50%.

N_C

(1) R_C = ( ---- )² R_T

N_T

N_C

(2) V_C = ---- V_T

N_T

N_T

(3) I_C = ---- I_T

N_C

where C and T subscripts refer to collector and transformer respectively.

Additional benefit of transformer is provision of impedance matching.

BJT Power Dissipation (P_D)

Given by

P_D = v_cbi_c + v_bei_e

» i_c(v_cb+v_be)

» v_cei_c

Consider a simple bias circuit:

V_CC V_CC V_CC²

P_Dmax = ------ ----- = ------

2R_C 2 4R_C

Therefore we require

V_CC²

------ < P_Dmax

4R_C

V_CC²

Therefore R_Cmin must be > ---------

4P_Dmax

For sinusoidal voltages and currents the average AC power can be calculated using one of the following relations:

P = V_RMSI_RMS = V_pI_p/2 = V_ppI_pp/8

= I_RMS²R = I_p²R/2 = I_pp²R/8

= V_RMS²/R = V_p²/2R = V_pp²/8R

where subscripts p and pp refer to peak and peak to peak respectively.

Class A Amplifier Current Drain

We need to be able to ensure that our amplifier stage supply is able to provide the required direct current. For our potential divider emitter resistor configuration there are two components to the current drain:

V_CC

- For a stiff voltage divider I₁ = ------

R₁+R₂

- Collector current drain I₂ = I_CQ

Sinusoidal variations average to zero, therefore with or without an input V_CC must supply an average current

V_CC

I_CC = I₁ + I₂ = ------- + I_CQ

R₁+R₂

Therefore, the total DC power supplied to the amplifier is

V_CC

P_CC = V_CCI_CC = V_CC(------- + I_CQ)

R₁+R₂

Efficiency for Class A Series Fed Amplifier

Instantaneous power from the DC supply is

P_s(t) = V_CCi = V_CC(I_Q + I_psin(wt))

= V_CCI_Q + V_CCI_psin(wt)

But since the average value of the sine term = 0

P_s = V_CCI_Q watts

The average signal power in the load R is

P_R = I_p²R/2

P_R I_p²R

\ h = ---- = --------

P_s 2V_CCI_Q

The maximum occurs when Q is centred

\ I_Q = I_pmax = V_CC/2R

(V_CC/2R)²R

\ h_max = --------------- = 0.25

2V_CC(V_CC/2R)

Class A Efficiency Discussions

Series Fed

Conventional maximum h = 0.25

Collector efficiency maximum h = 0.5

RC coupled

Optimum (R_C = Ö(2R_L)) h = 0.0858

Maximum power (R_C = R_L) h = 0.0833

Transformer/Inductor

collector emitter voltage swing » 2V_CC therefore choose transistor appropriately.

Maximum efficiency = 0.5

Class B

[Chirilian P718,722,782]

For class B amplifiers the DC bias current is very low compared with the output signal (biased at cut-off). Two transistors are usually combined to cope with sinusoidal input signals (one conducting on each half cycle), arranged in a "push-pull" configuration.

Class B amplifiers are used to satisfy the higher power requirements. However, the basic configurations can suffer from "crossover distortion".

Crossover Distortion

Crossover distortion and the need for transformer coupling can be eliminated by the use of modified push-pull stages.

Improved Class B Configurations

These make use of an intermediate bias arrangement "class AB". That is, biasing between class A and class B. Complementary-symmetry npn and pnp transistors connected as "emitter followers" are usually employed. The negative feedback has the effect of minimising distortion and providing impedance matching and power gain.

Crossover distortion can also be minimised using the circuits shown below.

Voltage-divider bias helps to minimise the dead-zone

Diode bias stabilization

The use of the diodes tend to bring the transistors into conduction earlier. Hence eliminating the "dead-zone".

Due to the large loop gain of the opertional amplifier arrangement.

This reduces the V_BE volt drops to the order of mV.

Class C

[Chirilian P876, S&B, Floyd P275]

Amplifiers are biased below cut-off.

Current flows near the peak of the input signal. The output signal would be distorted except for the action of its load. This is usually a tuned circuit, which therefore has a high resistive value at the frequency of interest. Hence, the selected signal output is free from non-linear distortions.

Input voltage and output current waveforms

Tuned class C amplifier with clamper bias

The base-emitter junction is biased into cut-off as a result of a negative charge on the capacitor. Oscillation occurs due to cyclic charge-discharge of L and C. Magnitude slowly decreases from maximum of 2V_CC. Oscillation sustained by input pulses.

Frequency of oscillation = 1/(2pÖ(LC)).

Resonant circuit action

Class C Amplitude Modulator

[Bogart P688]

v_s(t) = A_ssin(w_st)

v_c(t) = A_csin(w_ct)

We can show that v_o(t) is given by

A_csin(w_ct) + 0.5A_s[cos(w_c-w_s)t - cos(w_c+w_s)t]

LSB USB

N.B. No w_s term. v_o(t) consists of the carrier and upper and lower sideband components. This takes place at the transmitter and a similar process is carried out at the receiver to demodulate the signal.

v_s(t) is replaced by v_OT(t) and v_OR(t) is filtered. Used for frequencies > 20KHz so that inductor and capacitor can be kept small.

Class D

[Bogart, Smith P478, and Floyd P278]

The fundamental element is a pulse width modulator (PWM), which produces a train of pulses whose widths are proportional to the level of the amplifier's input signal.

For effective PWM:

(1) peak-to-peak sawtooth must be > peak-to-peak input

signal.

(2) frequency of sawtooth must be ³ 10 times the

maximum frequency of input signal.

Filter suppresses HF components and recovers the average value of the pulse train. Since the average value of pulses is proportional to pulse widths, the output of the filter is a waveform that increases and decreases with pulse width i.e. a duplicate of input. Negative feedback is included to reduce distortion.

The PWM is used to drive the output stage of the amplifier which is typically a totem pole arrangement acting as an inverter. (The advantage being that in both on and off states the load is being driven by a low impedance signal source.)

A MOSFET totem pole, used to switch heavy load currents

Like class C, class D requires a filter to extract the signal from the pulsed waveform. There are many frequency components therefore, we can not use tank tuned circuit. Thus, a low pass filter is used instead. The upper cut-off frequency is selected to be » highest signal frequency.

MOSFETs such as the VMOS are advantageous in this type of application due to:

(1) Turn on time is not delayed by minority carrier

storage.

(2) Not susceptible to thermal runaway.

(3) Larger input impedance makes driver design easier.

Main advantage of class D is potentially high h (»100%), obtained (like class C) by spending little time in the linear region and therefore reducing dissipation.

Main disadvantage is the need for a good low pass filter and the fact that high speed switching of heavy currents leads to noise due to electromagnetic coupling (electromagnetic interference - EMI).

A 100-W class-D amplifier

Integrated Circuit (IC) Power Amplifiers

There are a variety of very complex high performance implementations of these power amplifier circuits.

[Bogart P652]

P_D depends on packaging eg for mA741

- metal packaging 500mW

- DIP 300mW

- flatpack 570mW

These specifications require deratings in different ways above 700^oC.

Environmental and Thermal Considerations

Power transistors dissipate a large amount of power, which generates heat and causes the collector junction temperature to rise. The temperature rise must be kept within a safe, acceptable limit in order not to damage the device. The maximum allowable collector junction temperature of Si power transistors is in the range of 150 to 200^oC.

Thermal Considerations

With amplifiers that are less than 100% efficient an obvious problem arises. That is, how do we dissipate this power that has not been transferred to the load?

Several different factors need to be considered in order to answer this question.

Example illustrating heat transfer by conduction, radiation and convection

Facilitating approaches:

- conduction using heat sinks

- radiation using appropriate surfaces (black paint)

- convection using fans.

The electrical analog of a thermal system is shown below, where P_D, q and T are analogous to constant current, source resistance and voltage, respectively.

Manufacturer's data sheets usually specify the maximum operating junction temperature range, the junction-to-case thermal resistance q_JC, and the case-to-ambient thermal resistance q_CA.

Where q is in degrees Celsius per watt.

Usually the device is mounted on some form of "heat sink", such as mounting it on a chassis or some other metal surface, this helps lower the junction temperature. The case-to-sink thermal resistance is denoted q_CS, the total system is shown below.

P_D = DT/q as I = V/R

The thermal resistance is related to the power dissipation P_D by

T_J - T_A = P_D(q_JC + q_CS + q_SA)

or

T_J - T_A = P_D(q_JA)

where q_JA = q_JC + q_CS + q_SA

If there is no heat sink then

q_JA = q_JC + q_CA

Power Derating Curve

Since transistor case temperature cannot be held at ambient temperature, manufacturers provide a power-temperature derating curve, as shown below.

Where T_CO is the temperature at which derating begins, and this is not necessarily 25^oC; and (T_C)_max is in the range 150 to 200^oC for Si devices.

Note that since the curve is linear, manufacturers often supply the "derating factor" in watts/^oC plus some other parameters. Where the derating factor is 1/q_JC in this case.

Effect of Heat Sink

Heat Sink Comments

(1) Correct use can lead to an increase in the maximum power dissipation by several orders of magnitude.

(2) For very high power use air or water cooling.

(3) The case of the transistor is often connected to the collector. Therefore, remember to insulate it using a suitable washer and conducting paste.

(4) Mount heatsinks as specified for maximum efficiency.

Thermal resistance for heat sinks, washers and metals can be calculated from

rt

q = ---- ^oC/W

A

where

t = thickness of material

A = area of material

r = resistivity of material in ^oCin/W or ^oCm/W.

[Franco P470]

Safe Operating Area (SOA) for Power BJTs

(1) Maximum allowable collector current I_Cmax.

(2) Maximum power dissipation hyperbola.

v_CEi_C = P_Dmax (T_CO) - use derating as necessary.

(3) Secondary breakdown limit. Due to non-uniform current flow across the emitter base junction. This causes thermal hotspots which could lead to thermal runaway.

(4) The collector emitter breakdown voltage BV_CEO. If v_CE exceeds this value avalanche breakdown of the collector base junction may occur.

Parameter Values of Power Transistors

Owing to the large geometry of power devices the parameters of importance are quite different to those of small signal devices. The important ones are:

(1) At high currents, the exponential i_C - v_BE relationship exhibits a constant n=2,

i.e. i_C = I_S exp (v_BE/2V_T)

(2) b is low (30 to 80) and could be as low as 5, b has a positive temperature coefficient.

(3) At high currents r_b'_e becomes very small and r_bb' becomes important.

(4) f_T is low (a few MHz), C_b'_c is large (100s of pF) and C_b'_e is even larger.

(5) I_CBO is large (tens of mA) and doubles for every 10^oC rise in temperature.

(6) BV_CEO is typically 50-100V but can be as high as 500V.

(7) I_Cmax is typically a few amps but could be as large as 100A.

Effect of Temperature on Power MOSFETs

Plot shows:

- Zero temperature coefficient point for v_GS in the range of 4-6V.

- At high values of v_GS, i_D exhibits a negative temperature coefficient. Therefore the device will not suffer from thermal runaway in this region.

- At low values of v_GS, i_D has a positive temperature coefficient therefore appropriate biasing must be employed.

[Ghausi P286]

Thermal Stability

[Chirilian P801, Ryder, and Boylestad & Nashelsky]

For high power devices the variation of I_CBO with temperature may have a significant effect on circuit stability. We have assumed that T_D = P_Dq_DA + T_A. However, instability may result if

dP_D/dT_D > 1/q_DA

We can show that the thermal stability factor, S_ICBOT, should satisfy the approximate relationship

S_ICBOT < (0.21V_CEq_DAI_CBO)^-1.

This may set the limit on our bias stability factor

S_ICBOB » (1 + b)/(1+b[R_E/(R_B+R_E)])

Therefore, for satisfactory design we require that

S_ICBOB << S_ICBOT

Transistor Switch

Simple Switching with Transistors

In this type of application the device is being "switched" between two regions of operation, namely

(1) Cutoff - where both junctions (base emitter and

base collector in the case of BJTs) are

reversed biased.

(2) Saturation - where both junctions are forward

biased.

On/off switching means that the transistor must traverse the active region. Going from "on" to "off" is affected by charge storage problems.

The on time is given by

t_on = t_d + t_r

where t_d is the delay time between the application of the base drive and the time when I_c = 0.1I_Csat; and t_r is the rise time i.e. the time required for I_C to rise from 0.1 I_Csat to 0.9I_Csat.

The off time is given by

t_off = t_s + t_f

where t_s is the storage time, that is the time between the removal of the base drive and the time when I_C starts to fall towards 0; and t_f is the fall time i.e. the time required for I_C to fall from 0.9I_csat to 0.1I_Csat.

Transistor Switching Waveforms

Propagation Delay

[Millman P161]

t_pd,HL + t_pd,LH

t_pd = -----------------

2

[Ghausi P577]

Approximate linearised analysis shows that

(1) Delay time t_d is given by

V₁-V₀

t_d = t_d ln --------

V₁-0.7

where t_d = R_BC_ibo - reverse biased emitter base junction.

(2) Rise time t_r is given by

1-0.1/K 0.8

t_r = t₁ ln --------- » t₁ -----

1-0.9/K K

where

b₀(1+R_CC_ibow_T) b₀I_b

t₁ = ---------------- and K = ------ >1

w_T I_CS

(3) Storage time t_s is given by

1+K/M

t_s = t_s ln -------

1+1/M

where

w_Á+w_I b_I

t_s » -------------- » ---- (If w_Á>>w_I, b₀>>1)

w_Áw_I(1-Á₀Á_I) w_I

w_I and Á_I are alpha cut off frequency and DC alpha for the inverse active region and Á₀ and w_Á are for the normal active region. M is given by:

M = -I_b2(I_CS/b₀)

If K,M >> 1 then

t_s » t_s ln(1+K/M)

(4) Fall time t_f is given by

0.9I_CS+b₀I_b2 1+0.9/M

t_f = t₁ ln -------------- = t₁ ln ---------

0.1I_CS+b₀I_b2 1+0.1/M

0.8

» t₁ ----- if M>>1 (for large turn off overdrive)

M

Both types of switch suffer from delays at switch on and switch off.

For FETs these problems are minimised by the use of complementary connections.

In the case of BJTs there are a number of different options, including:

(1) a "speed-up" capacitor across R_B.

(2) clamping devices across the base collector junction.

(3) switching the input between positive and negative voltage levels.

(4) Emitter-coupled techniques.

Speed-up Capacitor

Has the effect of reducing t₁ and thus t_r and t_f and consequently t_on and t_off. The appropriate value of C_S can be evaluated using

1+R_CC_ibow_T

C_S = ------------

R_Bw_b

where R_B is chosen to drive the device sufficiently into saturation.

t_r can also be reduced by overdriving the transistor with a very large value of I_b, but this would also tend to increase t_s. Thus there would be no obvious benefit.

Schottky Diode and Emitter Coupling

Both techniques improve performance by avoiding saturation and thus reducing the storage time t_s.

Emitter-coupled inverter (current-mode circuit), which prevents the transistor from going into saturation

A Schottky-clamped diode to prevent the transistor from going into saturation

The enhancement MOSFET as a switch

The NMOS Inverter with Depletion-type NMOS Load

CMOS Inverter

Switching Inductive Loads

Consider the circuit where Z_C=R_C+jwL

[This is a typical example of a transistor being used to "switch" a load].

Assume that V_I1 and V_I0 are the input voltages to switch "on" and "off" respectively.

When V_I=V_I1 we want the collector to pass a current I_C1 (base current I_B1 ).

When V_I=V_I0 we want a collector current I_C0=0 (base current I_B0 ).

[We often assume V_BE0<0.6V and V_BE1>0.6V for Si]

The two conditions are:

(i) When V_I=V_I0 we require that

R₂

------- V_I0 < V_BE0

R₁+R₂

[I_B » 0 and I_C » 0]

(ii) When V_I=V_I1 the current flowing into the base (I_B1) must be ³ I_C1/h_FE. In which case the base emitter voltage will be V_BE1.

I₁, current in R₁, is (V_I1-V_BE1)/R₁

I₂, current in R₂, is V_BE1/R₂

I_C1

We require I₁-I₂ ³ ----- (= I_B1)

h_FE

What is the Collector Voltage?

If the load, Z_C, were purely resistive, the voltage would be V_CC-I_CR_C. But, the voltage across an inductor is Ldi/dt. When the circuit turns on, I_C = 0 at first;

Ldi_C di_C V_CC

------ = V_CC Þ ----- = -----

dt dt L

The current will rise until I_C1 is reached, in practice, due to the series resistance in the coil (R_C) the current will rise exponentially.

The voltage across the coil will therefore be:

di_C

V = L ----- + i_CR_C

dt

R_C limits the current when the transistor is in the "on" state. When the transistor switches off, the flow of current stops abruptly and in theory di_C/dt = Ñ. Hence a large voltage appears across the coil.

Before After

-------- -------

In practice, the voltage is not infinite, but it is very large and may easily damage the transistor. (The circuit will work, but only once !) The solution is to use a diode to conduct the current when the circuit is broken. Hence:-

Before After

-------- -------

Diode reverse biased Diode forward biased

When the transistor is "on" the coil conducts and the diode is reverse biased. When the transistor switches off, the diode is forward biased and current flows through it. Now there is no voltage source and

di_C

L ----- + i_CR = 0

dt

so the current falls exponentially to zero.

The advantage of using a transistor as a switch is the fact that it is thermally efficient and very little power is wasted.

Solution for a circuit using values:

h_FE=100, I_C1=50mA, V_I1=2V, V_BE1=0.8V and V_B0=0.6V

Results in a circuit as shown below:

A disadvantage of the use of the diode is that it lengthens the decay of current through the inductor.

For applications where a fast decay is important it may be better to use a resistor, R, instead. The value of R should be chosen so that V_CC+IR is less than the maximum voltage allowed across the switch.

For fastest decay, with a given maximum voltage, a zener diode could be used; giving a ramping down of current rather than an exponential decay.

For inductors driven from AC sources the diode protection will not work; since the diode will conductor on alternate half cycles. A good solution is to use an RC snubber circuit of the form shown below:

An alternative protection device is a metal oxide varistor, or transient suppressor; which behaves electrically like a bidirectional zener diode.

As well as protecting the circuit in question from transient damage there is additional benefit of reduced inductive spike interference to other devices.

Relative Merits of BJTs and FETs

BJTs have higher g_m which results in a higher voltage gain. More linear characteristics of BJT leads to larger signal swing without distortion.

Square law characteristics of FETs leads to use in modulators and mixers small signal applications.

FETs have higher input impedance and low noise. Therefore they are used in first stages for amplifying small voltages from high impedance sources.

For ICs use MOSFET because they are smaller, simpler and therefore cheaper.

FET easier to bias successfully,

FETs less vulnerable to radiation effects.

[Ghausi P141, Smith P513, Metzar, and Malvino P379-82, 357,368]

Comparison of MOS and Bipolar Power Transistors

[E & WW]

NMOS BIPOLAR

Majority-carrier Minority carrier device

device

No charge-storage Charge stored in the base

and collector

High switching speed; Low switching speed;

less tempertaure temperature sensitive

sensitive than

bipolar devices.

Drift current Diffusion current

(fast process) (slow process)

Voltage driven Current driven

Purely capacitive Low input impedance;

input impedance; DC current required

no DC current

required

Simple drive Complex drive circuitry

circuitry (resulting from high base

current requirements)

Predominantly Positive temperature coefficeint

negative temperature of collector current.

coefficient of drain

current

No thermal runaway Thermal runaway

Devices can be Devices cannot be easily

paralleled with paralleled because of V_BE

some precautions matching problems and local

current concentration

Less susceptible Susceptible to second

to second breakdown breakdown

Square-law I-V Exponential I-V

characteristics at characteristics

low current;

linear I-V

features at high

current

Greater linear More intermodulation

operation and and cross modulation

fewer harmonics products

High on resistance Low on resistance (low

and therefore saturation voltage)

larger conduction because of conductivity

loss modulation of high

resistivity drift region

Drain current Collector current

proportional to approximately proportional

channel width to emitter stripe and area

low High

transconductance transconductance

High breakdown High breakdown voltage

voltage as the as the result of a

result of a lightly doped region

lightly doped of a base collector

region of a channel blocking junction.

drain blocking

junction.

Operational Amplifier

Schematic diagram of 741 type OA

Advantages of IC Operational Amplifier (OA)

Occupies smaller volume and weighs less than discrete equivalent, contrast even greater in terms of actual chip size. Much more important is the greater reliability obtained from automatic manufacture and testing. For example soldering, which is a great cause of problems in discrete circuits, is only required on a few leads. The failure rate of the OA is approximately the same as each of the individual components that would have made up the circuit.

-Reduced costs and power consumption,

-Low drift because of close proximity of components,

-Spurious signals not picked up by interconnecting wire

between devices,

-Stray capacitance reduced and

-faster switching possible.

There are, however, power dissipation problems with these devices and discrete output stages are often required.

Surprisingly the cost of an OA IC is comparable with that of a discrete transistor.

Most small signal analogue circuits designed today use an OA as the basic active element, and resort to transistors only when an OA is unsuitable.

Ideal versus Typical Characteristics

Ideal 741

------- -------

(1) Voltage gain (A_OL or A) Ñ 2x10⁵

(2) Output impedance (Z_O) 0 75W

(3) Input impedance (Z_I) Ñ 2MW

(4) Offset current (I_OS) 0 20nA

(5) Offset voltage (V_OS) 0 2mV

(6) Bandwidth (BW) Ñ 1MHz

Ideal Models of OA

Ideally V_o = (V₊ - V_-) * A (A = gain).

Hence we would expect a typical response of the form shown below:

In practice the actual characteristics look more like the one shown below:

Limiting caused by the upper and lower supply voltage levels applied to the device, viz:

Upper and lower are usually positive and negative, respectively. (However, this is not always the case.)

Minimisation of Shortcomings

Although A ¹ Ñ, generally < 10% error will be caused if the overall closed loop gain (A_CL) of the circuit is limited to < 100.

In practice the main deviation from ideal performance occurs as a result of 4, 5, and 6 above.

Effect of I_OS can be minimised by reducing the size of the resistance seen from each input terminal.

V_OS is normally reduced towards zero by the use of special compensation techniques.

The bandwidth specification is obtained by measuring the maximum possible gain at given frequencies. As frequency increases the gain decreases proportionally. This is due to the fact that A * BW = constant, i.e. the "gain bandwidth product" relationship.

741 example

At no frequency can the voltage gain times the operating frequency exceed 1MHz, as shown below:

Frequency Maximum Possible

(Hz) gain

10 100K

100 10K

1K 1K

10K 100

100K 10

Hence for reasonable performance the 741 should only be used in the frequency range of 0-10KHz (~ audio range).

[Stanley 2nd eddition P145]

Open loop gain A(jw) = A_OL/(1+(jw/w_C))

Closed loop gain A_CL(jw) = A_CL(DC)/(1+(jf/b_CL))

Open loop frequency response of a 741C

OA Characteristics

In the design of circuits that are expected to exhibit stable operation over long time periods and wide temperature variations, the characteristics of OAs must be taken into account.

For example circuits may be required to respond identically to DC, audio and radio frequencies. High speed transients may need to be transmitted. Input levels may be in or below the mV level from signal sources with high output impedances.

Therefore both the AC and DC characteristics of the device must be considered.

DC Characteristics

The ideal OA draws no current from the source driving it. Both the inverting and non-inverting inputs look and respond identically. The circuit response does not vary with temperature. Real OAs do not work in this way. Current is drawn from the source.

There are slight differences in the way the 2 inputs respond to current and voltage. A real OA will shift its operating point with temperature.

Bias Currents

The two OA inputs are via two BJTs (or FETs) base (gate) terminals. In either case the transistors must be biased, and this takes current.

Input bias current is normally specified by the manufacturer as

I_B = (I_B+ + I_B-)/2

For typical BJT (741) I_B = 500nA

For typical FET I_B = 50pA

Bias currents can result in significant output voltages. Their effect can be compensated for by the use of a compensating resistor. An example of this is shown below:

Effective compensation can be applied if R_C = R_F __ R_I.

Offset Current

Bias current compensation will work if both bias currents are equal. But since input transistors cannot be made identical, there will always be some small difference, "offset current" given by

I_OS = _ I_B+ - I_B- _

(absolute value used because there is no way of knowing which is the largest).

For BJT OA I_OS = 200nA

For FET OA I_OS = 10pA

Even with bias current compensation, I_OS will produce an output voltage for zero input voltage.

This effect can be reduced by reducing the size of the feedback resistor R_F. This has the obvious disadvantage of both reducing the gain and the input impedance of the circuit.

A solution to the problem is to use a "T" feedback network.

This has the effect of producing a large feedback resistance

R_T²+2R_TR_S

R_F = -----------

R_S

and a low resistance to ground, as seen by the inverting input, of R_gnd=R_T+R_S __ R_T

To design a T network, choose R_T<<R_F/2

then calculate R_S=R_T²/(R_F-2R_T)

Offset Voltage

Even with the minimisation of bias current and offset current, an input voltage of zero may produce a non-zero output voltage. This effect is called the "offset voltage", and is usually represented as shown below:

This voltage is amplified along with the input signal. Its value can vary from device to device therefore fixed compensation is not possible.

Some OAs are provided with offset compensation pins, and this is usually the best way to compensate. When this is not the case then external balancing circuits may be used.

External Balancing Techniques

[Jacob P153, Irvine P82]

Inverting amplifier

Range = ±V R₂/R₁

Non-inverting amplifier

Range = ±V R₂/R₁

Gain = 1 + (R₅/(R₄+R₂))

Differential amplifier

R₂ = R₃+R₄

Range = ±V(R₅/R₄)(R₁/(R₁+R₃))

Drift

Bias currents, offset currents and offset voltage all change with temperature, i.e. they "drift".

I_OS drift is usually expressed in nA/^oC.

V_OS drift is usually expressed in mV/^oC.

There are very few circuit techniques that can be used to minimise the effect of drift. (Careful circuit layout, to keep OAs away from heat sources and forced air cooling are quite effective.)

However, if drift is likely to be a problem then use a device with a low drift specification.